The present invention relates generally to a method of producing a heterojunction bipolar semiconductor device, and in a particular embodiment, a bipolar transistor, and also to a method of producing a semiconductor device including a bipolar transistor having a SiGe base supported by an oppositely doped substrate.
To improve the operating speed of a bipolar transistor, it is important that the base layer be thin enough to minimize the time it takes electronic charges to move from the emitter to the collector, thereby minimizing the response time of the transistor, and have a high concentration of dopant in order to minimize base resistance. Typically, ion implantation technique is widely used to form a base layer. However, this technique has a problem of ion channeling, which limits the minimum thickness of the base layer to about 40 nm. Another disadvantage of ion implantation is that the Si/SiGe film is often damaged by the ions, and high temperature annealing is required which alters the concentration profile within the various layers of semiconductor material making up the transistor.
One known technique to avoid the above problem is to form a base layer using an epitaxial technique which precisely defines the base region and inherently has no problem of channelling because the dopants are placed in the semiconductor layer during growth. With this technique, it is possible to form a base layer having a thickness smaller than 30 nm and having an arbitrary impurity concentration or profile by incorporating an impurity directly into the base layer during the epitaxial growth process. Using this technique, a high-speed bipolar transistor having a maximum cut-off frequency fT as high as 50 GHz has been realized.
Although the bipolar transistor fabricated with the above technique has such a high maximum cut-off frequency fT as a result of the thin base, the engineering trade-off is high base resistance (Rb) which may limit the maximum frequency of oscillation fmax to 30-40 GHz.
To further increase the impurity concentration of the base layer to reduce the base resistance (Rb), it is required to increase not only the impurity concentration of the base layer but also that of the emitter layer so that a sufficiently high current gain (hFE) can be obtained.
However, the further increase in the impurity concentration of the emitter can cause a reduction in bandgap which in turn results in a reduction in the injection efficiency, a reduction in the emitter-base breakdown voltage, and an increase in the emitter-base junction charging time constant xcfx84EB. Since the requirements among these parameters conflict with each other, there is a limitation in the improvement in the operating speed.
Notwithstanding, this conflict can be avoided by employing a heterojunction between the emitter and base in which the bandgap of the emitter is different from that of the base. For example, silicon germanium (SiGe) having a narrower bandgap than silicon is used as a base material so as to form a practical heterojunction. In the heterojunction structure, the emitter can inject charge carriers with greater efficiency into the base than the emitter of the homogeneous junction structure. This makes it possible to achieve a sufficiently high current gain without increasing either the base resistance (Rb) or the emitter-base junction charging time constant xcfx84EB, and thus it is possible to realize a high-speed bipolar transistor having a maximum frequency of oscillation fmax as high as about 100 GHz.
To fabricate a heterojunction bipolar transistor, it is important to control the distributions of p-type impurity and germanium (Ge) across the base layer so that the Ge profile is formed at a precise location with respect to the p-n junction. As was stated earlier, transistor performance is greatly affected by the incorporation of Ge and the concentration profiles of the dopants. Moreover, the interaction of bandgap profile with the dopant profile is also an important factor in the overall design of the transistor and the performance. If the location of the Ge profilexe2x80x94that is, the concentration of Ge versus position with respect to the dopant position is not controlled precisely from wafer to wafer, or from manufacturing lot to manufacturing lot, or even across the wafer, then transistor performance will vary accordingly. In one area of the wafer, for example, transistors with excellent high-frequency response may be realized while at a different location, poor high-frequency response might be seen. Correspondingly, these differences in transistor performance may result in poor circuit yield, and increased circuit testing costs.
With reference to FIGS. 1A-1C, a conventional method of producing a junction bipolar transistor is described below.
As shown in FIG. 1A, an n+ buried collector layer 112 is formed on the surface of a silicon substrate 111 by means of solid-state diffusion or ion-implantation. An epitaxial layer 113 with an impurity concentration of 5xc3x971016 atoms/cm3 is then epitaxially grown thereon by means of an epitaxial growth technique. The epitaxial layer 113 is locally oxidized (for example by the LOCOS (local oxidation of silicon) method so as to form a device isolation oxide film 114. The surfaces of the epitaxial layer 113 and the device isolation oxide film 114 can be planarized. In addition, an ion implantation process is then performed either before oxidation or after so that a p+ device isolation diffusion layer 115 is formed under the device isolation oxide film 1114. Another ion implantation process is performed to form an n+ collector contact diffusion layer 116 connected to the n+ buried collector layer 112.
Then as shown in FIG. 1B, a 30 nm thick silicon germanium (Si0.8Ge0.2) film containing boron (B) acting as a p-type impurity with a concentration of about 3xc3x971019 atoms/cm3 is formed over the entire surface area of the epitaxial layer 113.
A 50 to 80 nm thick silicon film containing an n-type impurity with a concentration of about 3xc3x971018 atoms/cm0.3 is then formed thereon.
Ion implantation and activation annealing are then performed so as to dope the surface region of the emitter layer 118 with an n-type impurity to a high concentration (for example in the range from 1xc3x971020 atoms/cm3 to the solid solubility level) thereby forming an emitter contact layer 119. The activation annealing should be performed in the range from about 850xc2x0 C. to 900xc2x0 C. A base and an emitter on the base are then formed by means of a patterning technique.
Subsequently, as shown in FIG. 1C, an interlayer insulating film 121 is formed and then contact holes 122, 123, and 124 are formed in the interlayer insulating film 121. Electrodes 125, 126, and 127 are then formed such that these electrodes are in contact with the base layer 117, the emitter contact layer 119, and the collector contact diffusion layer 116, respectively, through the contact holes 122, 123, and 124.
In another (second) conventional technique, the base layer, the emitter layer, and the emitter contact layer are formed by means of a low-temperature epitaxial growth process.
In a still another (third) conventional technique, after epitaxially forming the base layer and the emitter layer, an n-type impurity region is formed by means of an ion implantation process.
In the first conventional technique, however, if the base layer is subjected to a heat treatment at a temperature higher than approximately 800xc2x0 C., diffusion of boron (B) and germanium (Ge) in the base layer occurs. If such a diffusion occurs, the base width will be expanded and discrepancy in position between the bandgap profile and the p-n junction will occur. Furthermore, since the base layer of silicon germanium (SiGe) has a thickness greater than the critical film thickness determined by the thermal equilibrium theory, the high-temperature heat treatment will introduce dislocations, which will result in a degradation in transistor performance.
As shown in FIG. 2, immediately after the formation of the base layer by means of the epitaxial growth technique, it has a boron concentration distribution limited within a narrow range represented by a broken line, which is coincident with the range of the silicon germanium mixed crystal. However, boron atoms (B) diffuse during heat treatment performed after the formation of the base layer. As a result, the boron distribution is spread as represented by a solid line. Thus, the heat treatment causes an increase in the base width, which makes it difficult to achieve a high-speed operation. In FIG. 2, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth across the emitter, the base, and the collector.
In the second example of the conventional technique described above, when the epitaxial growth is performed at a low temperature below 800xc2x0 C., the surface of silicon becomes chemically more inactive due to adsorption of group V elements with the increase in the concentration of n-type impurity contained in the [ambient] in which the epitaxial growth is performed. This leads to a great reduction in the growth rate to a level which is too low for practical production.
On the other hand, in the third conventional technique, heat treatment at a rather high temperature is required to activate the implanted ions and to remove damage induced in the crystal during the ion implantation process. During the crystal annealing process, interstitial silicon atoms are generated, which can result in an increase in the diffusivity of boron (B) by two or more orders of magnitude.
The generation of interstitial silicon atoms in the ion implantation process is also a problem when an emitter is formed of polysilicon. If in-situ doped polysilicon is employed, the problem of enhanced diffusion of boron (B) due to the generation of interstitial silicon can be avoided. However, it is difficult to grow polysilicon on silicon without having a native oxide layer at the interface between the silicon and the polysilicon. The formation of the native oxide results in an increase in the emitter resistance.
Furthermore, when a bipolar transistor having a shallow base layer is formed together with another type of device such as a MOS transistor on the same substrate if polysilicon is employed to form the gate electrode of the MOS transistor, and the emitter, base and collector electrodes of the bipolar transistor as well as a resistor element, the polysilicon is required to be doped with an impurity to a high enough concentration, and the impurity atoms have to be activated by high-temperature heat treatment.
However, the impurities incorporated into the Si and SiGe films can diffuse during the high-temperature heat treatment. Thus, even if the above thin films are formed by means of the epitaxial technique, the high-temperature heat treatment leads to changes in the impurity profiles. Thus the effective thicknesses of the films become different from their original thicknesses.
When an SiGe film is employed as the base layer, since the lattice constant of Ge is 4% greater than that of Si, an internal stress occurs at the interface between the Si substrate and the SiGe film formed on the Si substrate. Therefore, if heat treatment is performed after forming the SiGe film on the Si substrate, a plastic strain occurs in the SiGe film so that the above internal stress is relaxed. As a result, lattice defects are created in the SiGe film. Since the above internal stress increases with increasing the Ge content, the sensitivity to the heat treatment decreases with the increasing Ge content.
On the other hand, the bandgap decreases with the increasing Ge content and having the alloy under stress with respect to the underlying silicon. It is advantageous to preserve the stress in the film and incorporate the proper amount of Ge into the alloy in order to create the correct heterojunction.
As can be understood from the above discussion, the advantages of the shallow base layer (of SiGe or Si) formed by means of the epitaxial technique are lost by the heat treatment performed on the substrate after the formation of the shallow base layer.
It is an object of this invention to provide a method and device that overcomes most of the limitations of prior art devices and processes for fabrication of these devices.
It is a further object of this invention to provide a transistor having a SiGe layer deposited over a substrate of silicon wherein the SiGe layer does not require further doping after a covering polysilicon layer is applied thereto.
It is a further object of the invention to provide a multi-layered semiconductor device having a layer of SiGe wherein after the application of SiGe to a substrate of another type of material, the SiGe layer about a base region remains substantially unchanged in thickness and conductivity.
In accordance with the invention, a method of forming a semiconductor structure is provided comprising the steps of:
a) providing a semiconductor substrate;
b) providing a layer of SiGe over at least a region of the semiconductor substrate;
c) providing a mesa of over a portion of the SiGe layer;
d) depositing a polycrystalline silicon layer over the mesa and over lower adjacent regions of the SiGe layer;
e) planarizing the polycrystalline silicon layer to expose the mesa; and,
f) etching the mesa to expose a region of SiGe below.
In accordance with the invention method of forming a semiconductor structure is provided comprising the steps of:
a) providing a substrate of a first semiconductor type;
b) providing a second layer of a second type of semiconductor material over at least a region of the first semiconductor substrate;
c) providing a mesa of over a portion of the second layer, the mesa being a material that can bond to the second type of semiconductor and that can be etched by an etching source without etching the second type of semiconductor;
d) depositing a conductive layer over the mesa and over lower regions adjacent to the mesa that will not be etched by the etching source;
e) planarizing the conductive layer; and,
f) etching the mesa to expose a region of the second layer below.
In accordance with the invention there is further provided, a method of forming a semiconductor structure comprising the steps of:
a) providing a semiconductor substrate;
b) providing a layer of SiGe over at least a region of the semiconductor substrate;
c) providing a mesa over a portion of the SiGe layer;
d) depositing a polycrystalline silicon layer over the mesa and over lower adjacent regions of the SiGe layer;
e) exposing an upper surface of the mesa by removing the polycrystalline silicon layer over the mesa;
f) and removing the mesa to expose a region of SiGe below.
In accordance with another aspect of the invention, a semiconductor device is provided, comprising:
a silicon substrate forming one of a collector and an emitter, the substrate being of a first conductivity type;
a layer of SiGe of a second conductivity type covering at least a portion of the silicon substrate; and,
a first layer of polysilicon of the second conductivity type at least substantially supported by and covering a substantial portion of the SiGe layer with the exception of a window region, forming a SiGe base of the transistor; and, a second layer of polysilicon of the first conductivity type covering and contacting the SiGe base of the transistor said layer of polysilicon forming the other of the collector and the emitter.
In accordance with another aspect of the invention, a semiconductor device is provided, comprising:
a silicon layer of a first conductivity type;
a layer of SiGe of a second conductivity type covering at least a region of the silicon layer; and,
a first layer of polysilicon of the second conductivity type at least substantially supported by and covering a substantial portion of the SiGe layer with the exception of a small window; and, a second layer of polysilicon of the first conductivity type covering the window and contacting the SiGe layer.
In accordance with a different aspect of the invention, a method is provided of applying a semiconductor seed layer to a mixed topology substrate having regions of exposed semiconductor material and regions of exposed dielectric material, comprising the steps of:
disposing the substrate in a growth chamber and nucleating the seed layer by exposing the semiconductor material and dielectric material to an atmosphere of gases, the gases being presented at a predetermined flow rate, temperature and pressure, wherein the temperature is less than 600xc2x0 C., the pressure is less than 10xe2x88x922 mbar, and the flow rate is less than 5 sccm.
An embodiment of the invention further comprises the step of providing a multi-layered semiconductor device having a layer of SiGe wherein after the application of SiGe to a substrate of another type of material, the SiGe layer about a base region remains substantially unchanged in thickness and conductivity; alternatively, boron is prescribed in the profile in the base for diffusion into the profile we require to get the best transistor performance.